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1 75a, 600v magnum motor drives description the PW-83075P6, pw-84075p6 and pw-85075p6 are half- bridge drive modules which contain isolated switch drivers, a pair of solid state switches, an isolated power supply, current sensing feedback (pw-84075p6 only) and a regenerative clamp protection circuit (pw-85075p6 only). the three modules can be used, in any combination, to create drives for brush, brush- less dc motors or ac induction motors. the logic inputs and current sense signal are compatible with dsp/microprocessors and/or fpga/asic circuits used to control the motor drives. these modular drives are capable of operating from either 135vdc or 270vdc power source that is totally isolated from the logic input signals. the modules are fault tolerant from out- put shorts, loss of any or all power supplies and power supply sequencing. applications the high reliability and flexibility of these drives make them suit- able for military and aerospace applications. among the many applications are: actuator systems for primary and secondary flight controls on aircraft; fan and compressor motor drives for environmental conditioning; pump motors for fuel and hydraulic fluid; antenna and radar positioning; and thrust vector position control of missiles, drones, and rpvs. power supply sleep mode gate drive and fault control upper sc fault lower disable/reset i s o l a t i o n b a r r i e r power supply high drive low drive vbus+ output vbus- ov amp regen status regen low auto reset ov adj vcc vcc rtn regen bus- regen bus- vbus+ figure 1c. pw-85075p6 block diagram power supply sleep mode gate drive and fault control upper sc fault lower disable/reset i s o l a t i o n b a r r i e r power supply high drive low drive vbus+ output vbus- current amp current amp r sense oc fault vref i_absval rsense+ rsense- vcc vcc rtn vdd vdd rtn i_vout auto reset power supply vcc vcc rtn sleep mode gate drive and fault control upper sc fault lower disable/reset i s o l a t i o n b a r r i e r power supply high drive low drive vbus+ output vbus- auto reset figure 1a. PW-83075P6 block diagram figure 1b. pw-84075p6 block diagram features ? 600 vdc drive for 270 vdc motors ? 75 amps @25c, 50 amps @85c ? operates with brushless, brush and induction motors ? input to output ground isolation with floating output stage ? short circuit protection ? trapezoidal or sinusoidal compatible ? dsp/microprocessor compatible ? PW-83075P6 - half-bridge drive ? pw-84075p6 - half-bridge drive with current sense ? pw-85075p6 - half-bridge drive with regenerative clamp june 13, 2000 data device corporation
2 june 13, 2000 data device corporation table 1. pw-8x075p6 absolute maximum ratings (tc = +25c unless otherwise specified) parameter symbol value units ground isolation voltage (note 2) junction temperature, power devices storage temperature range peak output current (10 ms) continuous output current input logic voltage logic power-in supply voltage drive supply voltage v iso tj tcs i peak i o upper, lower, disable/reset, sleepmode, auto reset vcc vbus+ to vbus- 2500 +150 -65 to +125 150 75 5.5 5.5 600 vdc c c a a vdc vdc vdc table 2. pw-8x075p6 specifications (tc = +25c, vcc = vdd = 5v unless otherwise specified) parameter output stage drive supply voltage (motor) output switch transistors (each) continuous current drive peak current short circuit trip current (note 1) output voltage drop (igbt) flyback diode instant forward voltage reverse recovery time @ t j = +125 c reverse recovery peak current reverse leakage current @ t j = +25 c reverse leakage current @t j = +125 c vbus+ to vbus- i o i peak i sc v ce(sat) v f t rr irm i r i r unipolar/bipolar +25c case +85c case +85c case, 15 ms 5 s i o = 50a i o = 50a i o = 50a di/dt = 480a/s i f = 50a (90 c) vbus = 480vdc vbus = 480vdc symbol test conditions 0 200 min typ max units 270 350 2.2 1.7 175 19 30 600 75 50 100 400 2.6 1.9 33 325 17 vdc a a a a vdc vdc ns a a ma intermittent case operating temperature continuous case operating temperature junction temperature, other components tc t ci -55 to +100 -55 to +125 c c t j +125 c vdc ma 5.5 5.0 110 4.5 f = 25 khz vcc icc power and logic supply (pw83075p6 only) voltage current ns ns s ns ns ms khz 470 840 200 200 35 100 3.7 t d (on) t d (off) t s d t r t f tsleepu fpwm output switching characteristics (see figure 5) turn-on propagation delay turn-off propagation delay disable propagation delay turn-on rise time turn-off fall time sleep_mode delay output switching frequency 390 740 100 140 0 vdc vdc vdc a na a a a ma vdc vdc a ma 3.15 2.45 2.1 24 100 24 1.5 0.8 0.5 2.5 1.6 0.9 23 0.1 0 23 0 1.4 0.1 1.55 0.9 0.4 22 0 22 1.3 2.4 0.4 vcc = 4.5v vin = vcc vin = 0v vin = vcc vin = 0v vin = vcc vin = 0v vcc = 4.5v vin = vcc vin = 0v vih vil vhyst iih iil iih iil iih iil vih vil iih iil control inputs upper, lower, disable/reset auto reset high level input voltage low level input voltage hysteresis voltage upper, lower high level input current low level input current reset/disable high level input current low level input current auto_reset high level input current low level input current sleep_mode high level input voltage low level input voltage high level input current low level input current
3 june 13, 2000 data device corporation units max typ min symbol test condition parameter table 2. pw-8x075p6 specifications (tc = +25c, vcc = vdd = 5v unless otherwise specified) current amplifier i_vout trasnfer ratio i_vout gain error i_vout offset i_vout offset drift i_vout gain % i_vout offset % i_vout offset % drift i_vabs gain i_vabs gain error i_vabs offset i_vabs offset drift i_vabs gain % i_vabs offset % i_vabs offset % drift delay time bandwidth linear range oc_fault trip level reference voltage input current gvout evout vos tcvos gvout% vos%vref tcvos% gvabs evabs vosabs tcvosabs gvout% vosabs% vref tcvosabs% tdelay fbw irange ioc ivref vref = 5.0v vref = 5.0v vref = 5.0v 0a = vref/2 0a = 0v vref = 5.0v vref = 5.0v 0a = 0v -6 -30 -90 -0.6 -18 -8 -131 -90 -2.6 -18 20 75 29.76 0.595 59.52 1.19 9 30 50 85 0.26 6 30 110 0.6 22 8 131 110 2.6 22 20 95 1 mv/a % mv ppm/c %vref/a %vref ppm/vref/c mv/a % mv ppm/c %vref/a %vref ppm/vref/c s khz a a ma max typ min symbol test condition parameter table 3. pw-84075p6 specifications (tc= +25c vcc = vdd = 5v unless otherwise specified) units 5.5 200 20 5 11 136 10 4.5 8 vcc, vdd icc idd gate off / sleep mode 25khz gate pulsing power and logic supply voltage logic supply current current amplifier supply current v ma ma ma notes: 1. vbus+ to vbus- must be 3 10v (during short circuit) for short circuit protection to operate. 2. from vcc rtn to vbus+, vbus-, output, regen low, rsense+, rsense-. c in-lbs oz (gr) c/w c/w c c c +250 3 tbd 0.55 +150 +100 +125 0.5 0.8 -55 -55 -65 mechanical maximum lead soldering temp mounting torque weight thermal maximum thermal resistance - igbt - diode junction temperature range case operating temperature case storage temperature ts q jc q jc tj tc tcs each output switch s ms ms ns ms 202 3.0 100 1.0 100 40 tdead tdoff.auto tdon.auto tpw.reset tcycle.auto upper-lower deadtime auto_reset delay to output off auto_reset delay to output enabled reset pulsewidth to clear sc_fault cycle time between auto_reset retries a ma 24 23 10 22 5 vo = vcc vo = 0.4v iscflth iscfltl control outputs sc_fault high level current low level current 15 0.2 4 iocflth iocfltl vo = vdd vo = 0.8v oc_fault high level input current low level input current ua ma
introduction the pw-8x075p6 is a universal modular half-bridge motor drive intended for use with brush, brushless dc and ac induction motors in aerospace applications. the isolation barrier, which separates the power and control stage, attenuates the ground noise generated from high speed, high power switching. all signals from the control to the power sections are isolated from power and ground of the other section. this eliminates false triggering of the input signals and the need for creative grounding schemes. the isolation barrier also allows the user to operate the output stage from either unipolar or bipo- lar power supplies without level shifting the input signals. a built in power supply located in the control stage provides power to all electronics in the power stage. this eliminates the need for refresh cycles or external power supplies for the gate drive circuitry and allows switching duty cycles from 0 - 100%. pw-84075p6 provides current sensing of either motor current or dc bus current. this current signal can be used as a feedback signal in a servo drive to create a torque loop. the output power transistors are protected from a short circuit or overvoltage condition (requires pw-85075p6) applied to the out- put pins. when a short circuit condition is detected, the output transistor is shut down and a flag is active indicating a short has occurred. when an overvoltage condition is detected, the over- voltage switch is enabled and a external load dump resistor is connected across the high voltage bus. a status flag is active indicating an overvoltage condition has occurred. functional and pin descriptions: (for PW-83075P6, pw-84075p6 and pw-85075p6 unless noted) upper, lower the upper and lower are cmos schmitt-trigger inputs and control the gate drives of the output transistors. each input is elec- trically isolated from the output. a deadband, as shown in fig- 4 june 13, 2000 data device corporation max typ min symbol test condition parameter table 4. pw-85075p6 specifications (tc = +25c, vcc = vdd = 5v unless otherwise specified) units over voltage transistor continuous current drive peak current output voltage drop (igbt) reverse leakage @ t j = +25c reverse leakage @ t j = +125c over voltage flyback diode reverse leakage @ tc = +25c reverse leakage @ tc = +125c over voltage trip trip level hysteresis io i peak v ce ( sat ) ir ir ir ir vtrip vhyst +25c case +85c case +85c case, 15 ms 600 vdc 600 vdc 2.0 35 30 60 3.0 250 1.0 a a a vdc a ma 480 vdc 480 vdc no external adjustments 370 35 20 1 400 40 50 7 430 45 a ma vdc vdc thermal maximum thermal resistance q jc over voltage switch 0.7 0.85 c/w 5.5 250 5 11 137 4.5 vcc icc gate off/ sleep mode 25khz gate pulsing power and logic supply voltage current v ma ma ure 2, between upper and lower inputs is necessary to pre- vent output cross conduction. sc fault the sc fault output signal indicates when the output of the motor drive has experienced a short circuit condition. the signal is normally at a logic high (h). a transition to a logic low (l) will occur once a short circuit condition is detected. see short cir- cuit operation for more detail. disable / reset the disable/reset control input is cmos schmitt-trigger input and enables (reset) or disables the controller. when the dis- able/reset input receives a logic low (l) pulse for at least 0.1 s, the sc fault output will go high (h) indicating that the inter- nal circuitry has been enabled or reset. to reset the motor drive, a logic low (l) must be presented to the disable/reset inputs when the auto reset is inactive or at a logic high (h). auto reset when the auto reset is tied to sc fault, the protection circuit will reset automatically after the short circuit fault has occurred, enabling the output to respond to the input commands. see short circuit operation for more detail. short circuit operation the pw-8x075p6 outputs are completely short-circuit-protected from either a hard or soft short (required pw-84075 and some external circuit) to the vbus+ or vbus- lines. each output tran- sistor is individually short-circuit (hard) protected by circuitry that detects the desaturation voltage for that transistor during a short condition. once a hard short circuit condition is detected, the active output transistors are shutdown. if the auto reset is tied to sc fault, the circuit will auto reset, remove the short cir- cuit flag, and reactivate the output transistor within 40 to 100ms. vdc vdc k w s s 15.6 0.4 4.8 15 0.2 4.75 36 48 13.8 4.2 i0 = 0 i0 = 0 vohstatus volstatus rstatus tdon.status tdoff.status regen status (ref. to regen bus-) high level output voltage low level output voltage output resistance vtrip rise to status on delay vtrip fall status off delay
5 june 13, 2000 data device corporation 0.6 s min. 50% upper lower 50% 50% 0.6 s min. 50% figure 2. pw-8x075p6 dead band requirement if the short is still present, the circuit will repeat the shut down and auto reset until the short is clear. the users can use the disable/reset (h) to shut down the gate drivers if a short per- sists. the auto reset is inactive when it presented a logic high (h). protecting against a soft-short requires a pw-84075 (current sensing) and external circuitry. when a soft-short occurs, the external circuit can activate the sleepmode (h) and shut down the gate drivers. sleep mode the sleep mode input turns the internal power supply on or off. a logic high (h) on the sleep mode input disables the internal power supply, disabling the motor drive output. no damage will occur to the motor drive during turn on or turn off of the power sup- ply. additionally, no special power up sequence is required. a logic low (l) turns the power supply on and allows the motor drive to operate normally. vcc, vcc rtn the vcc and vcc rtn are power connections that supply input power to the internal power supply, the gate drive and fault con- trol circuits. vbus+, vbus- vbus+ and vbus- are the high voltage power connections to the output stage. the high voltage can be either unipolar, +v and ground or bipolar, +/- v. external capacitor filtering will be required. see ddc applications note an/h-6. output the output connects to one input of the motor and applies vbus+, vbus-, or high impedance to the motor based on the state of the control inputs. it is capable of sourcing or sinking up to 75 amps, and the output can withstand a short circuit to vbus+ or vbus- without any damage by automatically turning itself off (zstate). vdd, vdd rtn (applies to the pw-84075p6 only) the vdd and vdd rtn supply input power to the current ampli- fier. i_vout (applies to pw-84075p6 only) the voltage on the i_vout pin represents current passing through rsense in the direction shown in the block diagram.this i_vout voltage is scaled by the input voltage at vref, where i_vout = (vref/2) + (vref/150) * i_rsense where, i_rsense is current through rsense i_vout is electrically isolated from the output stage. when the power supply is shut down (sleep mode input high), the voltage at i_vout will indicate 0v. vref (applies to pw-84075p6 only) a voltage reference from an external source is connected to the vref pin to set the output voltage scale for i_vout. rsense+, rsense- (applies to pw-84075p6 only) these pins are across rsense and can be connected in series with the output, vbus+ or vbus- to measure current. the inter- nal connections to rsense are kelvin to minimize errors. however, these pins can be connected absolutely anywhere with- in the isolation restrictions on the pins (600v to power pins, 2500v to logic pins). i _absval (applies to pw-84075p6 only) the i_ absval output voltage is the absolute value of the i_vout voltage signal. the scale is 0 to vref for +/- current in rsense. oc fault (applies to pw-84075p6 only) the oc fault output is an open drain output which indicates that current flowing through rsense has exceeded the overcurrent threshold. once the fault threshold is exceeded, the output tran- sitions from open drain to low within 6 s. regen status (applies to pw-85075p6 only) the regen status pin is referenced to regen bus-. it indi- cates the state of the regen clamp switch, h = on, l = off. an external opto-isolator input can be connected between regen status and regen bus- to translate this status to logic circuits, if desired. ov adj (applies to pw-85075p6 only) the pw-85075p6 is internally set for a trip voltage of 400v. to set a different trip voltage, an external resistor is connected from the ov adj pin to either regen bus- or vbus+ pins (see fig- ures 4a and 4b). these pins are available on the control pins. this resistor should be selected for the voltage, vmax, for the overvoltage switch to turn on. 0 20 55 50 45 40 35 30 25 15 95 85 75 65 55 105 115 125 5 khz 25 khz 15 khz 20 khz 10 khz 60 65 70 75 45 35 25 35 khz 10 5 figure 3. pw-8x075p6 output phase current vs. maximum operating case temperature vbus+ = 270 vdc duty cycle = 50% tj(max) = 150c maximum operating case temperature, tc c output phase current, i avg (amps)
6 june 13, 2000 data device corporation ov switch off ov switch on v ov switch off ov switch on figure 4a. pw-8x075p6 typical over voltage trip vs. ov adjust setting with external resistor connected to regen bus- figure 4b. pw-8x075p6 typical over voltage trip vs. ov adjust setting with external resistor connected to vbus+ note : v h = hysteresis voltage note : v h = hysteresis voltage upper/lower 50% t f t r output 90% 10% 50% t d (on) t d (off) figure 5. pw-8x075p6 input/output timing relationship output upper lower disable/ reset sleep- mode z 0 0 0 1 vbus+ 1 0 0 1 vbus- 0 1 0 1 * 1 1 0 1 z x x 1 x z x x x 0 x = indicates that this input is irrelevant z = high impedance (off). * = illegal command that will cause one of the outputs to fault. table 5. pw-8x075p6 truth table note: vbus+ (27) and regen bus- (26) on the power-pin side are also connected to pin 22 and 17 on the control-pin side, respec- tively, for ease of connecting the external resistor. regen low, regen bus-(applies to pw-85075p6 only) an external load dump resistor is connected between regen low and vbus+. when vbus+ reaches the level set by the ov adj, the internal clamp circuit will apply the load dump resistor from vbus+ to the vbus-, thereby dissipating the regenerative energy in the external resistor. in addition, regen bus- has to be externally connected to vbus- for the clamp circuit to work properly. this connection (pcb traces or wire) has to be able to carry the regenerative current.
7 june 13, 2000 data device corporation position command position error position amp velocity command velocity error velocity amp torque command torque error current error amp pwm pw-8x075p6 3-module set hall signals 3-phase motor 3 6 torque loop velocity loop position loop + - + - + - figure 6. typical position and velocity control loop power dissipation (see figure 7) there are three major contributors to power dissipation in the motor driver: conduction losses, switching losses, and flyback diode losses. consider the following operating conditions vbus = +270v i oa = 40a (see figure 7); i ob = 50a (see figure 7) ton = 50 m s (see figure 7); t = 100s ( period ) v ce(sat) = 2.0v (see table 2, i o = 50a, t c = +25c) ts1 = 200ns (see figure 7); ts2 = 200ns (see figure 7) fo = 10khz (switching frequency) v f is the diode forward voltage, table 2, i o = 50a, t c = +25c v f (avg) = 1.35v 1. conduction losses (p c ) p c = i ave x v ce(sat) x (ton / t) i ave =(i ob + i oa ) / 2 i ave = (50a + 40a) / 2 = 45 p c = 45a x 2.0v x (50s / 100s) p c = 45w 2. switching losses (p s ) p s = (e on + e off ) x fo e on = ts1 x vbus x i oa / 6 e on = 200ns x 270v x 40a / 6 e on = .00045j e off = ts2 x vbus x i ob / 6 e off = 200ns x 270v x 50a / 6 e off = .00036j p s = 10000 x (.00045 + .00036) p s = 8.1w 3. flyback diode losses (pd) pd = i ave x v f (avg) x (1- (ton / t)) pdf = 45a x 1.35v x [1 - (50s / 100s)] pdf = 30.38w transistor power dissipation (p t ) to calculate the maximum power dissipation of the output tran- sistor / diode pair as a function of the case temperature, use the following equation. p q = p c + p s + pdf total hybrid power dissipation (p hybrid) to calculate total power dissipated in the hybrid add the power dissipation of each conducting transistor / diode pair. typically, only two transistor / diode pairs are conducting at any given time. 6 p total = s [ p qi ] where i = each transistor/diode pair i = 1 i ob t on i oa vbus i o t s2 t s1 figure 7. output characteristics
8 june 13, 2000 data device corporation table 5: pin assignments - preliminary (contact factory for latest pin assignment) 2 vcc vcc vcc pin # functions description 1 disable/reset disable/reset disable/reset 3 upper upper upper 4 vcc rtn vcc rtn vcc rtn 5 lower lower lower 6 sleep mode sleep mode sleep mode 7 sc fault sc fault sc fault 8 auto reset auto reset auto reset 17 nc vref regen bus- 18 nc i_vout regen status 19 nc i_absval nc 20 nc vdd ov adj 21 nc vdd rtn nc 22 nc oc fault vbus+ PW-83075P6 pw-84075p6 pw-85075p6 25 nc rsense- regen low 26 nc rsense+ regen bus- 27 vbus+ vbus+ vbus+ 28 output output output 29 vbus- vbus- vbus- applications: figure 9a shows an example of position and/or velocity control hook-up with inner torque loop using the digital signal processor (dsp) for motor control. using software, the dsp can be imple- mented with one of a range of several motor control algorithms, such as svm (space vector modulation) or other fo (field oriented) control depending on the specific application. figure 9b shows an example of torque control loop with regen- erative clamp protection using uc-1625, two pw-84075p6 and one pw-85075p6. two pw-84075p6 ( ? bridge with current sense) sense the current in motor phase a and c. i_absval pins on each of the pw-84075p6 can be tied together to gener- ate a single composite analog output which is compared to the torque commanded input to produce an error signal. uc1625 use this error signal to regulate the output current (or torque) by controlling the duty cycle of the output transistors. for the case when the resolver/syncho are available instead of hall-effect devices, the circuit shown in figure 9c converts the resolver (sin and cos) signals to hall signals which can used to commutate the output transistors. 23 nc nc nc 24 nc nc nc
9 june 13, 2000 data device corporation 1 3 5 7 2 4 6 8 17 19 21 18 20 22 0.65 max (16.51) 2.89 max (73.40) 1.48 max (37.59) pw-8x075p6-xxxx m agnum m otor d rive 29 28 27 26 25 0.125 ( 3.17) 0.738 (18.74 0.188 (4.77) 0.200 (5.08) side view top view 23 24 0.250 (6.35) 16 eq. pin 0.100 centers (2.54 centers) 0.025 sq. (16 places) (0.635) molded in metal insert (2 places) 0.250 x 0.03(thk) (5 places) (6.35 x 0.76) 0.220 (5.58) 0.115 dia (#4 screw) (2 places) (2.92 dia) 2.52 (64.00) 2.36 (59.94) 0.100 (2.54) 0.168 (4.26) s/n xxxx d/c xxxx tm 1.140 (28.95) .940 (23.87) 0.800 (20.32) 0.230 (5.84) 0.100 (typ) (2.54) 0.35 (8.89) 0.120 (3.04) figure 8. pw-8x075p6 outline notes: 1. dimensions are in inches (mm).
10 june 13, 2000 data device corporation +5v c10 + c11 motor power supply +270v r20 c8 + c9 power rtn motor sleep mode vcc upper lower sc fault disable/reset vcc rtn regen status ov adj vbus+ output vbus- regen low upper lower sc fault oc fault i_vout vref upper lower sc fault i_vout vref vbus+ output vbus- rsense+ rsense- vbus+ output vbus- rsense+ rsense- pw-85075p6 pw-84075p6 pw-84075p6 sleep mode sleep mode disable/reset disable/reset oc fault vcc vcc rtn vcc vcc rtn vdd vdd rtn vdd vdd rtn (4) r21 (4) auto reset auto reset auto reset regen bus- vref i_vout (a) ua la ub lb uc lc i_vout (c) dsp motor controller position or velocity command resolver r/d converter (see figure 8d) vcc vdd vdd rtn notes: 1. c8 is a ceramic capacitor and should be selected per ddc application note an/h-6, pw-82351 motor drive power supply , equation 1. 2. c9 is an electrolytic capacitor and should be selected per ddc application note an/h-6, pw-82351 motor drive power supply, equation 1 . 3. c10 is 22 f, 15 v electolytic capacitor. c11 is 0.1 f, 50 v ceramic capacitor. 4. resistance and power of r20, r21 is application specific. figure 9a. pw-8x075p6 position or velocity hook-up using dsp motor controller
11 june 13, 2000 data device corporation +15v +5v c10 + c11 motor power supply +270v r20 c8 + c9 power rtn r19 10k (8) r18 5k 0.01f c7 r17 10k 10m cr4 3.3v 1n746 cd4050 cd4049 +5v +5v c6 0.1f r15 10k r14 10k r13 10k +5v 19 11 18 14 hb hc ha hall supply +5v motor lm741 lm741 r8 10k (8) r11 r5 2k 1m r6 1k +5v command signal input r21 10k (8) 3.3v 1n746 cr5 10k (8) 10k 10k (8) 100 w lm741 r10 r12 r22 r9 10k (8) r23 cd4049 1/6 1/6 1/6 1/6 q1(9) sleep mode vcc upper lower sc fault disable/reset vcc rtn regen status ov adj vbus+ output vbus- regen low upper lower sc fault oc fault i_vout vref upper lower sc fault i_vout vref vbus+ output vbus- rsense+ rsense- vbus+ output vbus- rsense+ rsense- pw-85075p6 pw-84075p6 pw-84075p6 hall rtn 10k v- 10k v- v- 10k v- 5k 10k uc-1625 sleep mode sleep mode disable/reset disable/reset oc fault (10) (10) (10) (10) (11) (11) (11) (11) (11) (11) (11) (11) (11) vcc vcc rtn vcc vcc rtn vdd vdd rtn vdd vdd rtn (4) r21 (4) auto reset auto reset auto reset regen bus- i_absval i_absval notes: 1. c8 is a ceramic capacitor and should be selected per ddc application note an/h-6, pw-82351 motor drive power supply , equation 1. 2. c9 is an electrolytic capacitor and should be selected per ddc application note an/h-6, pw-82351 motor drive power supply, equation 1 . 3. c10 is 22 f, 15 v electrolytic capacitor. c11 is 0.1 f, 50 v ceramic capacitor. 4. resistance and power of r20 and r21 is application specific. 5. all resistors have a tolerance of 10%, unless otherwise specified. 6. the cd4050 converts the +15v logic output of the uc-1625 to +5v logic signals. 7. the cd4049 (or equivalent) inverts the upper signal from the uc-1625. 8. 1% or better, depending on required accuracy. 9. q 1 can be either irml2402 or irmu014 ir irld014. 10. these high impedance inputs and summing junctions of the operational amplifiers are highly sensitive to noise. 11. these grounds should be closely tied together to reduce ground noise effect. figure 9b. pw-8x075p6 torque hook-up using uc-1625 motor controller
12 june 13, 2000 data device corporation -vco vel -vsum cos -c +c bit 1 bit 2 bit 3 bit 4 bit 5 bit 6 bit 7 bit 8 bit 9 bit 10 bit 11 bit 12 bit 13 bit 14 bit 15 bit 16 cb sin -s +s agnd +ref u3 -ref gnd a b bit/ inh/ el/ em/ c26 0.1f c27 22f c28 0.1f c29 22f 15 40 +5v r27 120k c25 560pf r28 2.8 m c24 56pf 9 8 7 6 5 10 11 13 14 12 19 20 4 r24 20k r25 20k r26 20k 1 2 r35 10k r29 0.1k r30 0.1k rs rc r31 10k r32 1k 2n2907 +15v 21 cr7 39 18 3 +5v vpp pgm oe ce a0 26 24 33 31 37 35 25 23 29 27 10 9 6 5 8 7 25 24 4 3 a1 a2 a3 a4 a5 a6 a7 a8 a9 20 22 c30 0.1f +5v 27 1 a10 a11 a12 21 23 2 00 01 02 03 04 05 06 07 26 24 33 31 37 35 27c64 11 12 13 15 16 17 18 19 d0 d1 d2 d3 d4 d5 d6 d7 3 4 7 8 13 14 17 18 q0 q1 q2 q3 q4 q5 q6 q7 2 5 6 9 12 15 16 19 74hct374 clk d7 +5v 1 11 r33 10k hc hb ha +15 -15 gnd gnd sense sin c22 0.1f +15v c23 0.1f -15v 13 8 10 11 2 1 c20 0.1f c21 0.1f +15v +15v 16 2 3 20 19 1 4 1 2 3 4 5 6 u6 el2009 16 17 -5v 22 ddc rdc-19220 hall outputs digital position & velocity information which can be used by the dsp (figure 8a) to close the position and/or velocity loops resolver inputs figure 9c. resolver to hall signal conversion circuit
13 june 13, 2000 data device corporation data device corporation registered to iso 9001 file no. a5976 r e g i s t e r e d f i r m ? u printed in the u.s.a. the information in this data sheet is believed to be accurate; however, no responsibility is assumed by data device corporation for its use, and no license or rights are granted by implication or otherwise in connection therewith. specifications are subject to change without notice. 105 wilbur place, bohemia, new york 11716-2482 for technical support - 1-800-ddc-5757 ext. 7420 headquarters - tel: (631) 567-5600 ext. 7420, fax: (631) 567-7358 southeast - tel: (703) 450-7900, fax: (703) 450-6610 west coast - tel: (714) 895-9777, fax: (714) 895-4988 europe - tel: +44-(0)1635-811140, fax: +44-(0)1635-32264 asia/pacific - tel: +81-(0)3-3814-7688, fax: +81-(0)3-3814-7689 world wide web - http://www.ddc-web.com ordering information pw - 8 x 075 px - x x 0 process requirements: 0 = standard ddc procedures no, burn-in 2 = high reliability processing with burn-in temperature grade/data requirements: 1 = -55c to +125c 3 = -0c to +70c 4 = -55c to +125c with variables test data 8 = 0c to +70c with variables test data 9 = -55c to 85c voltage rating 6 = 600v current rating 075 = 75a features 3 = standard ? bridge 4 = standard ? bridge w/ current sense 5 = standard ? bridge w/ regenerative voltage clamp

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